/* * Corenet based SoC DS Setup * * Maintained by Kumar Gala (see MAINTAINERS for contact information) * * Copyright 2009-2011 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/kdev_t.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <asm/time.h> #include <asm/machdep.h> #include <asm/pci-bridge.h> #include <asm/ppc-pci.h> #include <mm/mmu_decl.h> #include <asm/prom.h> #include <asm/udbg.h> #include <asm/mpic.h> #include <linux/of_platform.h> #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> #include "smp.h" void __init corenet_ds_pic_init(void) { struct mpic *mpic; unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | MPIC_NO_RESET; if (ppc_md.get_irq == mpic_get_coreint_irq) flags |= MPIC_ENABLE_COREINT; mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC "); BUG_ON(mpic == NULL); mpic_init(mpic); } /* * Setup the architecture */ void __init corenet_ds_setup_arch(void) { mpc85xx_smp_init(); #if defined(CONFIG_PCI) && defined(CONFIG_PPC64) pci_devs_phb_init(); #endif fsl_pci_assign_primary(); swiotlb_detect_4g(); pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); } static const struct of_device_id of_device_ids[] = { { .compatible = "simple-bus" }, { .compatible = "fsl,srio", }, { .compatible = "fsl,p4080-pcie", }, { .compatible = "fsl,qoriq-pcie-v2.2", }, { .compatible = "fsl,qoriq-pcie-v2.3", }, { .compatible = "fsl,qoriq-pcie-v2.4", }, { .compatible = "fsl,qoriq-pcie-v3.0", }, /* The following two are for the Freescale hypervisor */ { .name = "hypervisor", }, { .name = "handles", }, {} }; int __init corenet_ds_publish_devices(void) { return of_platform_bus_probe(NULL, of_device_ids, NULL); }