/* * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields * * Copyright (C) 2009-2010 Texas Instruments, Inc. * * Benoit Cousson (b-cousson@ti.com) * Santosh Shilimkar (santosh.shilimkar@ti.com) * * This file is automatically generated from the OMAP hardware databases. * We respectfully ask that any modifications to this file be coordinated * with the public linux-omap@vger.kernel.org mailing list and the * authors above to ensure that the autogeneration scripts are kept * up-to-date with the file contents. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H /* Base address */ #define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 /* Registers offset */ #define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000 #define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004 #define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010 #define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c #define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614 #define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618 #define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c /* Registers shifts and masks */ /* IP_REVISION */ #define OMAP4_IP_REV_SCHEME_SHIFT 30 #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) #define OMAP4_IP_REV_FUNC_SHIFT 16 #define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) #define OMAP4_IP_REV_RTL_SHIFT 11 #define OMAP4_IP_REV_RTL_MASK (0x1f << 11) #define OMAP4_IP_REV_MAJOR_SHIFT 8 #define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) #define OMAP4_IP_REV_CUSTOM_SHIFT 6 #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) #define OMAP4_IP_REV_MINOR_SHIFT 0 #define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) /* IP_HWINFO */ #define OMAP4_IP_HWINFO_SHIFT 0 #define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) /* IP_SYSCONFIG */ #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) /* PADCONF_WAKEUPEVENT_0 */ #define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24 #define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24) #define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23 #define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23) #define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22 #define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22) #define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21 #define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21) #define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20 #define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20) #define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19 #define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19) #define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18 #define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18) #define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17 #define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17) #define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16 #define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16) #define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15 #define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15) #define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14 #define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14) #define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13 #define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13) #define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12 #define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12) #define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11 #define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11) #define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 #define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) #define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9 #define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9) #define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8 #define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8) #define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7 #define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7) #define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6 #define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6) #define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5 #define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5) #define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4 #define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4) #define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3 #define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3) #define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2 #define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2) #define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 #define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) #define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0 #define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0) /* CONTROL_SMART1NOPMIO_PADCONF_0 */ #define OMAP4_FREF_DR0_SC_SHIFT 30 #define OMAP4_FREF_DR0_SC_MASK (0x3 << 30) #define OMAP4_FREF_DR1_SC_SHIFT 28 #define OMAP4_FREF_DR1_SC_MASK (0x3 << 28) #define OMAP4_FREF_DR4_SC_SHIFT 26 #define OMAP4_FREF_DR4_SC_MASK (0x3 << 26) #define OMAP4_FREF_DR5_SC_SHIFT 24 #define OMAP4_FREF_DR5_SC_MASK (0x3 << 24) #define OMAP4_FREF_DR6_SC_SHIFT 22 #define OMAP4_FREF_DR6_SC_MASK (0x3 << 22) #define OMAP4_FREF_DR7_SC_SHIFT 20 #define OMAP4_FREF_DR7_SC_MASK (0x3 << 20) #define OMAP4_GPIO_DR7_SC_SHIFT 18 #define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18) #define OMAP4_DPM_DR0_SC_SHIFT 14 #define OMAP4_DPM_DR0_SC_MASK (0x3 << 14) #define OMAP4_SIM_DR0_SC_SHIFT 12 #define OMAP4_SIM_DR0_SC_MASK (0x3 << 12) /* CONTROL_SMART1NOPMIO_PADCONF_1 */ #define OMAP4_FREF_DR0_LB_SHIFT 30 #define OMAP4_FREF_DR0_LB_MASK (0x3 << 30) #define OMAP4_FREF_DR1_LB_SHIFT 28 #define OMAP4_FREF_DR1_LB_MASK (0x3 << 28) #define OMAP4_FREF_DR4_LB_SHIFT 26 #define OMAP4_FREF_DR4_LB_MASK (0x3 << 26) #define OMAP4_FREF_DR5_LB_SHIFT 24 #define OMAP4_FREF_DR5_LB_MASK (0x3 << 24) #define OMAP4_FREF_DR6_LB_SHIFT 22 #define OMAP4_FREF_DR6_LB_MASK (0x3 << 22) #define OMAP4_FREF_DR7_LB_SHIFT 20 #define OMAP4_FREF_DR7_LB_MASK (0x3 << 20) #define OMAP4_GPIO_DR7_LB_SHIFT 18 #define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18) #define OMAP4_DPM_DR0_LB_SHIFT 14 #define OMAP4_DPM_DR0_LB_MASK (0x3 << 14) #define OMAP4_SIM_DR0_LB_SHIFT 12 #define OMAP4_SIM_DR0_LB_MASK (0x3 << 12) /* CONTROL_PADCONF_MODE */ #define OMAP4_VDDS_DV_FREF_SHIFT 31 #define OMAP4_VDDS_DV_FREF_MASK (1 << 31) #define OMAP4_VDDS_DV_BANK2_SHIFT 30 #define OMAP4_VDDS_DV_BANK2_MASK (1 << 30) /* CONTROL_XTAL_OSCILLATOR */ #define OMAP4_OSCILLATOR_BOOST_SHIFT 31 #define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31) #define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30 #define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30) /* CONTROL_USIMIO */ #define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31 #define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31) #define OMAP4_PAD_USIM_RST_LOW_SHIFT 29 #define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29) #define OMAP4_USIM_PWRDNZ_SHIFT 28 #define OMAP4_USIM_PWRDNZ_MASK (1 << 28) /* CONTROL_I2C_2 */ #define OMAP4_SR_SDA_GLFENB_SHIFT 31 #define OMAP4_SR_SDA_GLFENB_MASK (1 << 31) #define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29 #define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29) #define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28 #define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28) #define OMAP4_SR_SCL_GLFENB_SHIFT 27 #define OMAP4_SR_SCL_GLFENB_MASK (1 << 27) #define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25 #define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25) #define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24 #define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24) /* CONTROL_JTAG */ #define OMAP4_JTAG_NTRST_EN_SHIFT 31 #define OMAP4_JTAG_NTRST_EN_MASK (1 << 31) #define OMAP4_JTAG_TCK_EN_SHIFT 30 #define OMAP4_JTAG_TCK_EN_MASK (1 << 30) #define OMAP4_JTAG_RTCK_EN_SHIFT 29 #define OMAP4_JTAG_RTCK_EN_MASK (1 << 29) #define OMAP4_JTAG_TDI_EN_SHIFT 28 #define OMAP4_JTAG_TDI_EN_MASK (1 << 28) #define OMAP4_JTAG_TDO_EN_SHIFT 27 #define OMAP4_JTAG_TDO_EN_MASK (1 << 27) /* CONTROL_SYS */ #define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31 #define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31) /* WKUP_CONTROL_SPARE_RW */ #define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0 #define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0) /* WKUP_CONTROL_SPARE_R */ #define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0 #define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0) /* WKUP_CONTROL_SPARE_R_C0 */ #define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31 #define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31) #define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30 #define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30) #define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29 #define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29) #define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28 #define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28) #define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27 #define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27) #define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26 #define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26) #define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25 #define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25) #define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24 #define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24) #endif