// Copyright 2015, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of ARM Limited nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------
#ifndef VIXL_SIM_FCVTNU_XD_TRACE_AARCH64_H_
#define VIXL_SIM_FCVTNU_XD_TRACE_AARCH64_H_
const uint64_t kExpected_fcvtnu_xd[] = {
0u,
0u,
0u,
0u,
1u,
1u,
1u,
1u,
2u,
10u,
18446744073709551615u,
18446744073709551615u,
0u,
0u,
0u,
18446744073709551615u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
18446744073709551615u,
0u,
1u,
1u,
1u,
1u,
1u,
1u,
1u,
1u,
1u,
1u,
1u,
1u,
1u,
1u,
18446744073709551615u,
18446744073709551615u,
18446744073709551615u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
4503599627370496u,
4503599627370497u,
4503599627370498u,
4503599627370499u,
8987183256397123u,
9007199254740988u,
9007199254740989u,
9007199254740990u,
9007199254740991u,
2251799813685248u,
2251799813685248u,
2251799813685249u,
2251799813685250u,
4493591628198562u,
4503599627370494u,
4503599627370494u,
4503599627370495u,
4503599627370496u,
1125899906842624u,
1125899906842624u,
1125899906842624u,
1125899906842625u,
2246795814099281u,
2251799813685247u,
2251799813685247u,
2251799813685248u,
2251799813685248u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
9223372036854774784u,
9223372036854775808u,
18446744073709549568u,
18446744073709551615u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
0u,
2147483646u,
2147483646u,
2147483646u,
2147483646u,
2147483646u,
2147483647u,
2147483647u,
2147483647u,
2147483647u,
2147483647u,
2147483648u,
2147483648u,
4294967294u,
4294967294u,
4294967294u,
4294967294u,
4294967294u,
4294967295u,
4294967295u,
4294967295u,
4294967295u,
4294967295u,
4294967296u,
4294967296u,
};
const unsigned kExpectedCount_fcvtnu_xd = 207;
#endif // VIXL_SIM_FCVTNU_XD_TRACE_AARCH64_H_