// Copyright 2016, VIXL authors
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
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// Test description for instructions of the following forms:
// MNEMONIC{<c>}{<q>} {<Rd>}, <Rm>, <Rs>
// MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> }
// MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> }
//
// Note that this test only covers the cases where the optional shift
// operand is not provided. The shift operands are tested in
// "cond-rd-rn-operand-rm-shift-amount-*-a32.json".
{
"mnemonics": [
"Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
// ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
"Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
// ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
"And", // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Rsb", // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Rsc", // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Sbc", // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
"Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
// SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
"Subs", // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
// SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
"Sxtab", // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
"Sxtab16", // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
"Sxtah", // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
"Uxtab", // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
"Uxtab16", // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
"Uxtah", // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
// Shift instructions that alias to MOV.
// Note that we are not giving them a different input for their
// last operand since they are already tested in
// "cond-rd-operand-rn-shift-rs-a32.json".
"Asr", // ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
"Asrs", // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
"Lsl", // LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
"Lsls", // LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
"Lsr", // LSR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
"Lsrs", // LSRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
"Ror", // ROR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
"Rors" // RORS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
],
"description": {
"operands": [
{
"name": "cond",
"type": "Condition"
},
{
"name": "rd",
"type": "AllRegistersButPC"
},
{
"name": "rn",
"type": "AllRegistersButPC"
},
{
"name": "op",
"wrapper": "Operand",
"operands": [
{
"name": "rm",
"type": "AllRegistersButPC"
}
]
}
],
"inputs": [
{
"name": "apsr",
"type": "NZCV"
},
{
"name": "rd",
"type": "Register"
},
{
"name": "rn",
"type": "Register"
},
{
"name": "rm",
"type": "Register"
}
]
},
"test-files": [
{
"type": "assembler",
"test-cases": [
{
"name": "Operands",
"operands": [
"cond", "rd", "rn", "rm"
],
"operand-limit": 500
}
]
},
{
"type": "simulator",
"test-cases": [
{
"name": "Condition",
"operands": [
"cond"
],
"inputs": [
"apsr"
]
},
// Test combinations of registers values with rd == rn.
{
"name": "RdIsRn",
"operands": [
"rd", "rn", "rm"
],
"inputs": [
"rd", "rn", "rm"
],
"operand-filter": "rd == rn and rn != rm",
"operand-limit": 10,
"input-filter": "rd == rn",
"input-limit": 200
},
// Test combinations of registers values with rd == rm.
{
"name": "RdIsRm",
"operands": [
"rd", "rn", "rm"
],
"inputs": [
"rd", "rn", "rm"
],
"operand-filter": "rd == rm and rn != rm",
"operand-limit": 10,
"input-filter": "rd == rm",
"input-limit": 200
},
// Test combinations of registers values.
{
"name": "RdIsNotRnIsNotRm",
"operands": [
"rd", "rn", "rm"
],
"inputs": [
"rd", "rn", "rm"
],
"operand-filter": "rd != rn != rm",
"operand-limit": 10,
"input-limit": 200
}
]
}
]
}