CHIPSET(0x29A2, I965_G, i965)
CHIPSET(0x2992, I965_Q, i965)
CHIPSET(0x2982, I965_G_1, i965)
CHIPSET(0x2972, I946_GZ, i965)
CHIPSET(0x2A02, I965_GM, i965)
CHIPSET(0x2A12, I965_GME, i965)
CHIPSET(0x2A42, GM45_GM, g4x)
CHIPSET(0x2E02, IGD_E_G, g4x)
CHIPSET(0x2E12, Q45_G, g4x)
CHIPSET(0x2E22, G45_G, g4x)
CHIPSET(0x2E32, G41_G, g4x)
CHIPSET(0x2E42, B43_G, g4x)
CHIPSET(0x2E92, B43_G1, g4x)
CHIPSET(0x0042, ILD_G, ilk)
CHIPSET(0x0046, ILM_G, ilk)
CHIPSET(0x0102, SANDYBRIDGE_GT1, snb_gt1)
CHIPSET(0x0112, SANDYBRIDGE_GT2, snb_gt2)
CHIPSET(0x0122, SANDYBRIDGE_GT2_PLUS, snb_gt2)
CHIPSET(0x0106, SANDYBRIDGE_M_GT1, snb_gt1)
CHIPSET(0x0116, SANDYBRIDGE_M_GT2, snb_gt2)
CHIPSET(0x0126, SANDYBRIDGE_M_GT2_PLUS, snb_gt2)
CHIPSET(0x010A, SANDYBRIDGE_S, snb_gt1)
CHIPSET(0x0152, IVYBRIDGE_GT1, ivb_gt1)
CHIPSET(0x0162, IVYBRIDGE_GT2, ivb_gt2)
CHIPSET(0x0156, IVYBRIDGE_M_GT1, ivb_gt1)
CHIPSET(0x0166, IVYBRIDGE_M_GT2, ivb_gt2)
CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)
CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2)
CHIPSET(0x0402, HASWELL_GT1, hsw_gt1)
CHIPSET(0x0412, HASWELL_GT2, hsw_gt2)
CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2)
CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1)
CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2)
CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1)
CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2)
CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2)
CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1)
CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2)
CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2)
CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1)
CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2)
CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1)
CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2)
CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2)
CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1)
CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2)
CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2)
CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1)
CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2)
CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1)
CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2)
CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1)
CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2)
CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1)
CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2)
CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1)
CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2)
CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)