// Copyright 2015, ARM Limited
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
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//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------

#ifndef VIXL_SIM_FCVTMU_XS_TRACE_A64_H_
#define VIXL_SIM_FCVTMU_XS_TRACE_A64_H_

const uint64_t kExpected_fcvtmu_xs[] = {
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  1u,
  1u,
  1u,
  10u,
  0u,
  18446744073709551615u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  8388608u,
  8388609u,
  8388610u,
  8388611u,
  16143410u,
  16777212u,
  16777213u,
  16777214u,
  16777215u,
  4194304u,
  4194304u,
  4194305u,
  4194305u,
  8071705u,
  8388606u,
  8388606u,
  8388607u,
  8388607u,
  2097152u,
  2097152u,
  2097152u,
  2097152u,
  4035852u,
  4194303u,
  4194303u,
  4194303u,
  4194303u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  0u,
  9223371487098961920u,
  9223372036854775808u,
  18446742974197923840u,
  18446744073709551615u,
  0u,
  0u,
  0u,
  2147483520u,
  2147483648u,
};
const unsigned kExpectedCount_fcvtmu_xs = 104;

#endif  // VIXL_SIM_FCVTMU_XS_TRACE_A64_H_