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// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
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//     used to endorse or promote products derived from this software without
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// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------

#ifndef VIXL_SIM_FCVTNS_XS_TRACE_A64_H_
#define VIXL_SIM_FCVTNS_XS_TRACE_A64_H_

const int64_t kExpected_fcvtns_xs[] = {
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(1),
  INT64_C(1),
  INT64_C(1),
  INT64_C(1),
  INT64_C(2),
  INT64_C(10),
  INT64_C(0),
  INT64_C(9223372036854775807),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  -INT64_C(1),
  -INT64_C(1),
  -INT64_C(1),
  -INT64_C(1),
  -INT64_C(2),
  -INT64_C(10),
  INT64_C(0),
  -INT64_C(9223372036854775807) - 1,
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(0),
  INT64_C(8388608),
  INT64_C(8388609),
  INT64_C(8388610),
  INT64_C(8388611),
  INT64_C(16143410),
  INT64_C(16777212),
  INT64_C(16777213),
  INT64_C(16777214),
  INT64_C(16777215),
  INT64_C(4194304),
  INT64_C(4194304),
  INT64_C(4194305),
  INT64_C(4194306),
  INT64_C(8071705),
  INT64_C(8388606),
  INT64_C(8388606),
  INT64_C(8388607),
  INT64_C(8388608),
  INT64_C(2097152),
  INT64_C(2097152),
  INT64_C(2097152),
  INT64_C(2097153),
  INT64_C(4035852),
  INT64_C(4194303),
  INT64_C(4194303),
  INT64_C(4194304),
  INT64_C(4194304),
  -INT64_C(8388608),
  -INT64_C(8388609),
  -INT64_C(8388610),
  -INT64_C(8388611),
  -INT64_C(16143410),
  -INT64_C(16777212),
  -INT64_C(16777213),
  -INT64_C(16777214),
  -INT64_C(16777215),
  -INT64_C(4194304),
  -INT64_C(4194304),
  -INT64_C(4194305),
  -INT64_C(4194306),
  -INT64_C(8071705),
  -INT64_C(8388606),
  -INT64_C(8388606),
  -INT64_C(8388607),
  -INT64_C(8388608),
  -INT64_C(2097152),
  -INT64_C(2097152),
  -INT64_C(2097152),
  -INT64_C(2097153),
  -INT64_C(4035852),
  -INT64_C(4194303),
  -INT64_C(4194303),
  -INT64_C(4194304),
  -INT64_C(4194304),
  -INT64_C(9223372036854775807) - 1,
  -INT64_C(9223372036854775807) - 1,
  -INT64_C(9223371487098961920),
  INT64_C(9223371487098961920),
  INT64_C(9223372036854775807),
  INT64_C(9223372036854775807),
  INT64_C(9223372036854775807),
  -INT64_C(2147483904),
  -INT64_C(2147483648),
  -INT64_C(2147483520),
  INT64_C(2147483520),
  INT64_C(2147483648),
};
const unsigned kExpectedCount_fcvtns_xs = 104;

#endif  // VIXL_SIM_FCVTNS_XS_TRACE_A64_H_